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rev. 0 a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002 AD9975 broadband modem mixed-signal front end features low cost, 3.3 v-cmos, mixed signal, front end converter for broadband modems 10-bit d/a converter (txdac+ ) 50 msps input word rate 2 interpolating low-pass transmit filter 100 msps dac output update rate wide (21 mhz) transmit bandwidth power-down modes 10-bit, 50 msps a/d converter fourth order lpf with selectable cutoff frequency dual mode programmable gain amplifier internal clock multiplier (pll) two auxiliary clock outputs 48-lead lqfp package applications powerline networking home phone networking functional block diagram txen rxen txclk rxclk adio[9:0] sport oscin xtal AD9975 pga lpf pga adc register control 3 3 10 clk-gen tx dac+ k 10 10 agc[ 2:0] tx+ tx clk1 clk2 rx+ rx general description the AD9975 is a single-supply, broadband modem, mixed signal, front end (mxfe) ic. the device contains a transmit path interpolation filter and dac and a receive path pga, lpf, and adc required for a variety of broadband modem applications. also on-chip is a pll clock multiplier that pro- vides all required clocks from a single crystal or clock input. the txdac+ uses a digital 2 interpolation low-pass filter to oversample the transmit data and ease the complexity of analog reconstruction filtering. the transmit path bandwidth is 21 mhz when sampled at 100 msps. the 10-bit dac provides differen- tial current outputs. the dac full-scale current can be adjusted from 2 to 20 ma by a single resistor, providing 20 db of additional gain range. the receive path consists of a pga, lpf, and adc. the program- mable gain amplifier (pga) has two modes of operation. one mode allows programming through the serial port and provides a gain range from ? db to +36 db in 2 db steps. the other mode allows the gain to be controlled through an asynchronous 3-pin port and offers a gain range from 0 db to 48 db in 8 db steps with the use of an external gain stage. the receive path lpf cutoff frequency can be selected to either 12 mhz or 26 mhz. the filter cutoff frequency can also be tuned or bypassed where filter requirements differ. the 10-bit adc uses a multistage differential pipeline architecture to achieve excellent dynamic performance with low power consumption. the digital transmit and receive ports are multiplexed onto a 10-bit databus and have individual tx/rx clocks and tx/rx enable lines. this interface connects directly to homelug 1.0 phy/mac chips from intellon and conexant. the AD9975 is available in a space-saving 48-lead lqfp pack- age. the device is specified over the commercial (?0 c to +85 c) temperature range. txdac+ is a registered trademark and mxfe is a trademark of analog devices, inc.
rev. 0 ? AD9975?pecifications test parameter temp level min typ max unit osc in characteristics frequency range full i 10 50 mhz duty cycle 25 cii 40 50 60 % input capacitance 25 c iii 3 pf input impedance 25 c iii 100 m ? clock output characteristics clka jitter (f clka derived from pll) 25 cii 14 ps rms clka duty cycle 25 c iii 50 5% tx characteristics 2 interpolation filter characteristics tx path latency, 2 interpolation full ii 30 f dac cycles pass-band flatness 0 mhz to 20.7 mhz full ii 0.8 db stop-band rejection @ 29.3 mhz full ii 35 db txdac resolution full ii 10 bits conversion rate full ii 10 100 mhz full-scale output current full ii 2 10 20 ma voltage compliance range (tx+ or tx?avss) full ii ?.5 +1.5 v gain error 25 ci i ?.5 2+ 5.0 %fs output offset 25 cii 0 2 tbd a differential nonlinearity 25 c iii 0.5 lsb integral nonlinearity 25 cii 1 lsb output capacitance 25 c iii 5 pf phase noise @ 1 khz offset, 10 mhz signal 25 c iii ?00 dbc/hz signal-to-noise and distortion (sinad) 5 mhz analog out (20 mhz bw) 25 ci i ?0.6 db wideband sfdr (to nyquist, 50 mhz max) 25 c iii 5 mhz analog out 25 c iii ?6.2 dbc narrowband sfdr (3 mhz window) 5 mhz analog out 25 c iii ?7.9 dbc imd (f1 = 6.25 mhz, f2 = 7.8125 mhz) 25 c iii ?7 dbfs rx path characteristics (lfp bypassed) resolution n/a n/a 10 bits conversion rate full ii 10 50 mhz pipeline delay, adc clock cycles n/a n/a 5.5 cycles dynamic performance (a in = ?.5 dbfs, f = 5 mhz) @ f oscin = 50 mhz, rx lpf bypassed signal-to-noise and distortion ratio (sinad) full iii ?6.6 db effective number of bits (enob) full iii 9.1 bits signal-to-noise ratio (snr) full iii ?9.2 db total harmonic distortion (thd) full iii ?0.1 db spurious-free dynamic range (sfdr) full iii ?6 db rx path gain/offset minimum programmable gain 25 ci 6 db maximum programmable gain narrow band rx lpf or rx lpf bypassed 25 ci +36 db wideband rx lpf 25 ci +30 db gain step size 25 ci 2 db gain step accuracy 25 cii 0.4 db gain range error full ii 1.0 db absolute gain error, pga gain = 0 db full ii 0.8 db rx path input characteristics input voltage range (gain = ? db) full iii 4 vppd input capacitance 25 c iii 4 pf differential input resistance 25 c iii 270 ? input bandwidth (? db) (rx lpf bypassed) 25 c iii 50 mhz input referred noise (at +36 db gain with filter) 25? iii 16 v rms input referred noise (at ? db gain with filter) 25? iii 684 v rms common-mode rejection 25? iii 40 db (v s = 3.3 v 10%, f oscin = 50 mhz, f dac = 100 mhz, gain = ? db, r set = 4.02 k , 100 dac load.)
rev. 0 AD9975 ? test parameter temp level min typ max unit rx path lpf (low cutoff frequency) cutoff frequency full iii 12 mhz cutoff frequency variation full iii 7% attenuation @ 22 mhz full iii 20 db pass-band ripple full ii 1.0 db group delay variation full ii 30 ns settling time (to 1% fs, min to max gain change) 25 cii 150 ns total harmonic distortion at max gain (thd) full i ?1 dbc rx path lpf (high cutoff frequency) cutoff frequency full iii 26 mhz cutoff frequency variation full iii 7% attenuation @ 35 mhz full iii 20 db pass-band ripple full ii 1.2 db group delay variation full ii 15 ns settling time (to 1% fs, min to max gain change) 25 cii 80 ns total harmonic distortion at max gain (thd) full i ?1 dbc rx path digital hpf latency (adc clock source cycles) 1 cycle roll-off in stop band 6 db/octave ? db frequency f adc /400 hz power-down/disable timing power-down delay (active-to-power-down) dac 25 cii 200 ns interpolator 25 cii 200 ns power-up delay (power-down-to-active) dac 25 cii 10 s pll 25 cii 10 s adc 25 ci i 1000 s pga 25 cii 1 s lpf 25 cii 1 s interpolator 25 cii 200 ns minimum reset pulsewidth low (t rl ) full iii 5 f oscin cycles adio port interface maximum input word rate 25 ci 100 mhz tx-data setup time (t su )25 cii 3.0 ns tx-hold hold time (t hd )25 cii 0 ns rx-data valid time(t vt )25 cii 3.0 ns rx-data hold time (t ht )25 cii 1.5 ns
rev. 0 ? AD9975 specifications (continued) test parameter temp level min typ max unit serial control bus maximum sclk frequency (f sclk ) full ii 25 mhz clock pulsewidth high (t pwh ) full ii 18 ns clock pulsewidth low (t pwl ) full ii 18 ns clock rise/fall time full ii 10 s data/chip-select setup time (t ds ) full ii 25 ns data hold time (t dh ) full ii 0 ns data valid time (t dv ) full ii 20 ns cmos logic inputs logic ??voltage 25 cii v drvdd ?0.7 v logic ??voltage 25 cii 0.4 v logic ??current 25 cii 12 a logic ??current 25 cii 12 a input capacitance 25 c iii 3 pf cmos logic outputs (1 ma load) logic ??voltage full ii v drvdd ?0.6 v logic ??voltage 25 cii 0.4 v digital output rise/fall time full ii 1.5 2.5 ns power supply all blocks powered up i s_total (total supply current) 25 ci 210 227 ma digital supply current (i drvdd + i dvdd )25 c iii 22.5 ma clock supply current (i clkvdd )25 c iii 5.5 ma analog supply current (i avdd )25 c iii 182 ma power consumption of functional blocks rx lpf 25 c iii 110 ma adc and spga 25 c iii 55 ma rx reference 25 c iii 2 ma interpolator 25 c iii 20 ma dac 25 c iii 18 ma pll-a 25 c iii 22 all blocks powered down i s_total (total supply current) 25 ci 21 27 ma digital supply current (i drvdd + i dvdd )25 c iii 10 ma clock supply current (i clkvdd )25 c iii 0 ma analog supply current (i avdd )25 c iii 11 ma specifications subject to change without notice. absolute maximum ratings * power supply (v s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 v digital output current . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ma digital inputs . . . . . . . . . . . . . . . . ?.3 v to drvdd + 0.3 v analog inputs . . . . . . . . . . . . . . . . . ?.3 v to avdd + 0.3 v operating temperature . . . . . . . . . . . . . . . . . . ?0 c to +85 c maximum junction temperature . . . . . . . . . . . . . . . . . 150 c storage temperature . . . . . . . . . . . . . . . . . . ?5 c to +150 c lead temperature (soldering 10 sec) . . . . . . . . . . . . . . 300 c * absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired. functional operability under any of these conditions is not necessarily implied. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. explanation of test levels i. devices are 100% production tested at 25 c and guaranteed by design and characterization testing for the commercial operating temperature range (?0 c to +85 c). ii. parameter is guaranteed by design and/or characterization testing. iii. parameter is a typical value only. thermal characteristics thermal resistance 48-lead lqfp ja = 57?/w jc = 28?/w
rev. 0 AD9975 C5C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9975 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device pin configuration 1 osc in 2 senable 3 sclk 4 sdata 5 av d d 6 a vss 7 tx+ 8 tx 9 a vss 10 fs adj 11 refio 12 clkvdd 36 drvss 35 drvdd 34 rxboost/sdo 33 clkout2 32 rxclk 31 txclk 30 txen 29 rxen 28 adio0 27 adio1 26 adio2 25 adio3 13 d vss 14 dvdd 15 a gc2 16 a gc1 17 a gc0 18 clkout1 19 adio9 20 adio8 21 adio7 22 adio6 23 adio5 24 adio4 48 xtal 47 av d d 46 a vss 45 rx 44 rx+ 43 a vss 42 a vss 41 reft 40 refb 39 a vss 38 av d d 37 reset AD9975 48-pin lqfp top view (not to scale) pin function description pin no. mnemonic function 1o sc in crystal oscillator inverter input 2 senable serial bus enable input 3 sclk serial bus clock input 4 sdata serial bus data i/o 5, 38, 47 avdd analog 3.3 v power supply 6, 9, 39, 42, avss analog ground 43, 46 7t x+ transmit dac + output 8 tx transmit dac ?output 10 fs adj dac full-scale output current adjust with external resistor 11 refio dac band gap decoupling node 12 clkvdd power supply for clkout1 13 dvss digital ground 14 dvdd digital 3.3 v power supply 15?7 agc[2:0] agc control inputs 18 clkout1 auxiliary clock output 19?8 adio[9:0] digital data i/o port 29 rxen adio direction control input 30 txen tx path enable 31 txclk adio sample clock input 32 rxclk adio request clock input 33 clkout2 auxiliary clock output 34 rxboost/ external gain control output/ sdo serial data output 35 drvdd digital i/o 3.3 v power supply 36 drvss digital i/o ground 37 reset reset input 40, 41 refb, reft adc reference decoupling node 44 rx+ receive path + input 45 rx receive path ?input 48 xtal crystal oscillator inverter output ordering guide model temperature range package description package option AD9975abst ?0? to +85? 48-lead lqfp st-48 AD9975absteb ?0? to +85? AD9975 eval board AD9975abstrl ?0? to +85? AD9975abst reel
rev. 0 ? AD9975 definitions of specifications clock jitter the clock jitter is a measure of the intrinsic jitter of the pll generated clocks. it is a measure of the jitter from one rising edge of the clock with respect to another edge of the clock nine cycles later. differential nonlinearity error (dnl, no missing codes) an ideal converter exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guaranteed no missing codes to 10-bit resolution indicate that all 1024 codes, respectively, must be present over all operating ranges. integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from ?egative full scale?through ?ositive full scale.?the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. phase noise single-sideband phase noise power density is specified relative to the carrier (dbc/hz) at a given frequency offset (1 khz) from the carrier. phase noise can be measured directly on a generated single tone with a spectrum analyzer that supports noise marker measurements. it detects the relative power between the carrier and the offset (1 khz) sideband noise and takes the resolution bandwidth (rbw) into account by subtracting 10 log(rbw). it also adds a correction factor that compensates for the implementation of the resolution bandwidth, log display, and detector characteristic. output compliance range the range of allowable voltage at the output of a current-output dac. operation beyond the maximum compliance limits may cause either output stage saturation, resulting in nonlinear per- formance, or breakdown. spurious-free dynamic range (sfdr) the difference, in db, between the rms amplitude of the dac? output signal (or adc? input signal) and the peak spurious signal over the specified bandwidth (nyquist bandwidth, unless otherwise noted). pipeline delay (latency) the number of clock cycles between conversion initiation and the associated output data being made available. offset error first transition should occur for an analog value 1/2 lsb above negative full scale. offset error is defined as the deviation of the actual transition from that point. gain error the first code transition should occur at an analog value 1/2 lsb above negative full scale. the last transition should occur for an analog value 1 1/2 lsb below the nominal full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. input referred noise the rms output noise is measured using histogram techniques. the adc output code? standard deviation is calculated in lsb and converted to an equivalent voltage. this results in a noise figure that can directly be referred to the rx input of the AD9975. signal-to-noise and distortion ratio (sinad) sinad is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. effective number of bits (enob) for a sine wave, sinad can be expressed in terms of the number of bits. using the following formula, n sinad db = (.)/. 176 602 it is possible to get a measure of performance expressed as n , the effective number of bits. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured input signal and is expressed as a percentage or in decibels. power supply rejection power supply rejection specifies the converter? maximum full-scale change when the supplies are varied from nominal to minimum and maximum specified voltages.
rev. 0 t ypical performance characteristics?d9975 ? f sample 10 0 0.2 0.4 0.6 0.8 1.0 magnitude ?db ?0 ?0 ?0 ?00 0 ?0 ?0 ?0 ?0 0.1 0.3 0.5 0.7 0.9 ?0 ?0 interpolation filter including sin(x)/x tpc 1. 2 low-pass interpolation filter f s ?mhz 10 0 0.2 0.4 0.6 0.8 1.0 magnitude ?db ?0 ?0 ?0 ?00 0 ?0 ?0 ?0 ?0 0.1 0.3 0.5 0.7 0.9 ?0 ?0 interpolation filter including sin(x)/x tpc 2. 2 band-pass interpolation filter, f s /2 modulation, adjacent image preserved frequency ?mhz 01020 30 40 magnitude ?dbc ?0 ?0 ?0 ?00 0 ?0 ?0 ?0 ?0 515253545 ?0 ?0 tpc 3. single tone spectral plot @ f data = 50 msps, f out = 5 mhz, 2 lpf frequency ?mhz 01020 30 40 magnitude ?dbc ?0 ?0 ?0 ?00 0 ?0 ?0 ?0 ?0 515253545 ?0 ?0 tpc 4. single tone spectral plot @ f data = 50 msps, f out = 11 mhz, 2 lpf frequency ?mhz 10 10.0 10.4 10.8 11.2 11.6 12.0 dbc ?0 ?0 ?0 ?00 0 ?0 ?0 ?0 ?0 1.02 10.6 11.0 11.4 11.8 ?0 ?0 tpc 5. dual tone spectral plot @ f data = 50 msps, f out = 6.7 mhz and 7.3 mhz, 2 lpf frequency ?mhz ?0 0 magnitude ?dbc ?4 ?6 ?2 4 123 56789 11121314151617181920 10 ?8 ?0 ?2 ?4 ?6 ?8 ?0 third order harmonic second order harmonic tpc 6. harmonic distortion vs. f out @f data = 50 msps
rev. 0 ? AD9975 frequency ?mhz 10 10.003 10.005 10.007 10.009 10.011 10.013 dbc ?0 ?0 ?0 ?00 0 ?0 ?0 ?0 ?0 10.004 10.006 10.008 10.010 10.012 ?0 ?0 tpc 7. phase noise plot @f data 50 msps, f out = 10 mhz, 2 lpf frequency ?mhz 10 3 dbc ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 57911 13 15 17 19 21 23 tpc 8. ?n-band?multitone spectral plot @f data = 50 msps, f out = k 195 khz, 2 lpf frequency ?mhz 10 1 dbc ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 11 21 31 41 51 61 71 81 91 101 tpc 9. ?ide-band?multitone spectral plot @f data = 50 msps, f out = k 195 khz, 2 lpf tuning target ?decimal 35 frequency ?mhz 30 192 25 20 208 224 240 255 tpc 10. f c vs. tuning target, f adc = 50 mhz, lpf = wideband rx filter tuning target ?decimal 20 frequency ?mhz 18 192 12 10 208 224 240 255 16 14 tpc 11. f c vs. tuning target, f adc = 50 mhz, lpf = narrowband rx filter 0.60 ? ?.20 ?.80 0.20 ?.60 0 0.40 ?.40 36 gain accuracy ?db vg a gain ?db ? ? 0246810121416182022242628303234 tpc 12. pga gain error vs. gain
rev. 0 AD9975 ? 2.5 ? 1.8 1.5 2.1 1.6 1.9 2.3 1.7 36 offset ?lsbs vg a gain ?db ? ? 0246810121416182022242628303234 2.4 2.0 2.2 tpc 13. pga gain step vs. gain 1mhz 10mhz 100mhz 12.1mhz 0 log mag 5db/div ?.0db ref 0db tpc 14. rx lpf frequency response, lpf = narrowband rx filter, f adc = 50 mhz, tuning target = 255 9.9mhz 1mhz 10mhz 100mhz 0 delay 10ns/div 70.1ns ref 0s tpc 15. rx lpf frequency response, lpf = wideband rx filter, f adc = 50 mhz, tuning target = 255 24.1mhz 1mhz 10mhz 100mhz 0 log mag ref 0db ?.0db 5db/div tpc 16. rx lpf group delay, lpf = narrowband rx filter, f adc = 50 mhz, tuning target = 255 22.1mhz 1mhz 10mhz 100mhz 0 delay 5 ns/div ref 0s 33.9ns tpc 17. rx lpf group delay, lpf = wideband rx filter, f adc = 50 mhz, tuning target = 255 123.5 khz 0 log mag 5db/div ref 0db ?.00db 10khz 100khz 1mhz tpc 18. rx hpf frequency response, f adc = 50 mhz
rev. 0 ?0 AD9975 4000 1 3000 2400 3600 2600 3200 2800 adc output code adc clock cycles 3400 3800 5913 17 21 25 29 33 37 tpc 19. rx path settling, 1/2 scale rising step with gain change, lpf f c = 26 mhz, f adc = 50 mhz 4000 1 3000 2400 3600 2600 3200 2800 adc output code adc clock cycles 3400 3800 5913 17 21 25 29 33 37 tpc 20. rx path settling, 1/2 scale falling step with gain change, lpf f c = 26 mhz, f adc = 50 mhz 20 8.75 9.50 9.00 8.50 enobs f s ?mhz 9.25 25 30 40 50 35 45 tpc 21. rx path enob vs. f adc , f in = 5 mhz, gain = ? db, rx lpf bypassed 20 56 59 57 55 magnitude ?db f s ?mhz 58 25 30 40 50 35 45 60 tpc 22. rx path snr vs. f adc , f in = 5 mhz, gain = ? db, rx lpf bypassed 20 ?0 ?5 magnitude ?db f s ?mhz 25 30 40 50 35 45 ?5 tpc 23. rx path thd vs. f adc , f in = 5 mhz, gain = ? db, rx lpf bypassed 0 8.7 9.3 8.9 8.5 enobs f in ?mhz 9.1 26 14 18 10 16 9.5 4812 20 tpc 24. rx path enob vs. f in , f adc = 50 mhz, gain = ? db, rx lpf bypassed
rev. 0 AD9975 ?1 0 51 54 52 50 magnitude ?db f in ?mhz 53 26 14 18 10 16 55 4812 20 56 57 58 tpc 25. rx path snr vs. f in , f adc = 50 mhz, gain = ? db, rx lpf bypassed 0 ?0 ?5 ?5 ?5 magnitude ?db f in ?mhz ?0 26 14 18 10 16 ?0 4812 20 tpc 26. rx path thd vs. f in , f adc = 50 mhz, gain = ? db, rx lpf bypassed
rev. 0 ?2 AD9975 transmit path the AD9975 transmit path consists of a digital interface port, a bypassable 2 interpolation filter, and a transmit dac. the clock signals required by these blocks are generated by the inter- nal pll. the block diagram below shows the interconnection between the major functional components of the transmit path. interpolation filter the interpolation filter can be programmed to run at a 2 upsampling ratio in either a low-pass filter or band-pass filter mode. the transfer functions of these two modes are shown in tpc 1 and tpc 2, respectively. the y-axes of the figures show the magnitude response of the filters in db, and the x-axes show the frequency normalized to f dac . the top trace of the plot shows the discrete time transfer function of the interpolation filter. the bottom trace shows the tx path transfer function including the sin(x)/x transfer function of the dac. in addition to the two upsampling modes, the interpolation filter can be programmed into a pass-through mode if no interpolation filtering is desired. the table below shows the following parameters as a function of the mode in which it is programmed. latency ?the number of clock cycles from the time a digital impulse is written to the dac until the peak value is output at the tx+ and tx?pins. flush ?the number of clock cycles from the time a digital impulse is written to the dac until the output at the tx+ and tx?pins settles to zero. f pass ?the frequency band over which the pass-band ripple is less than the stated magnitude (i.e., 0.1 db or 1.0 db). f stop ?the frequency band over which the stop-band attenuation is greater than the stated magnitude (i.e., 40 db or 50 db). table i. interpolation filters vs. mode register 7[7:4] 0x1 0x5 mode 2 lpf 2 bpf, adj. image latency, f dac clock cycles 30 30 flush, f dac clock cycles 48 48 f pass , 0.1 db <0.204 >0.296, <0.704 f pass , 1.0 db <0.207 >0.293, <0.707 f stop , 40 db <0.296 >0.204, <0.796 f stop , 50 db <0.302 <0.198, >0.802 dpll-a clock distribution figure 1 shows the clock signals used in the transmit path. the dac sampling clock, f dac , is generated by dpll-a. f dac has a frequency equal to l f oscin , where l is the pll clock multiplier value and f oscin is the frequency of the input to pll-a. the value of l is programmed through the serial interface port and can be set to 1, 2, 4, or 8. the transmit path expects a new input sample at the adio interface at a rate of f dac /2 if the interpolation filter is being used. if the interpolation filter is bypassed, the transmit path expects a new input sample at the adio interface at a rate of f dac. d/a converter the AD9975 dac provides differential output current on the tx+ and tx?pins. the values of the output currents are comple- mentary, m eaning they will always sum to i fs , the full-scale current of the dac. for example, when the current from tx+ is at full scale, the current from tx?is zero. the two currents will typically drive a resistive load that will convert the output currents to a voltage. the tx+ and tx?output currents are inherently ground seeking and should each be connected to matching resistors, r l , that are tied directly to agnd. the full-scale output current of the dac is set by the value of the resistor placed from the fs adj pin to agnd. the rela- tionship between the resistor, r set , and the full-scale output current is governed by the following equation: ir fs set = 39 4 ./ the full-scale current can be set from 2 to 20 ma. generally, there is a trade-off between dac performance and power consumption. the best dac performance will be realized at an i fs of 20 ma. however, the value of i fs adds directly to the overall current consumption of the device. the single-ended voltage outputs appearing at the tx+ and tx?nodes are: vir tx tx l ++ = vir tx tx l = note that the full-scale voltage of v tx + and v tx ? should not exceed the maximum output compliance range of 1.5 v to pre- vent signal compression. to maintain optimum distortion and linearity performance, the maximum voltages at v tx + and v tx should not exceed 0.5 v. the single-ended full-scale voltage at either output node will be: vir fs fs l = the differential voltage, v diff , appearing across v tx+ and v tx is: viir diff tx tx l = + () and vir diff fs fs l _ = it should be noted that the differential output impedance of the dac is 2 r l and any load connected across the two output resistors will load down the output voltage accordingly.
rev. 0 AD9975 ?3 receive path description the receive path consists of a two stage pga, a continuous time, 4-pole lpf, an adc, and a digital hpf. also working in conjunction with the receive path is an offset correction circuit and a digital phase-locked loop. each of these blocks will be discussed in detail in the following sections. programmable gain amplifier the pga has a programmable gain range from ? db to +36 db if the narrower (approximately 12 mhz) lpf bandwidth is selected, or if the lpf is bypassed. if the wider (approximately 29 mhz) lpf bandwidth is selected, the gain range is ? db to +30 db. the pga is comprised of two sections, a continuous time pga (cpga), and a switched capacitor pga (spga). the cpga has possible gain settings of 0, 6, 12, 18, 24 and 30. the spga has possible gain settings of ? db, ? db, ? db, 0 db, +2 db, +4 db, and +6 db. table ii shows how the gain is distributed for each programmed gain setting. the cpga input appears at the device rx+ and rx?input pins. the input impedance of this stage is nominally 270 ? differential and is not gain dependent. it is best to ac-couple the input signal to this stage and let the inputs self-bias. this will lower the offset voltage of the input signal, which is important at higher gains, since any offset will lower the output compliance range of the cpga output. when the inputs are driven by direct coupling, the dc level should be avdd/2. however, this could lead to larger dc offsets and reduce the dynamic range of the rx path. there are two modes for selecting the rx path gain. the first mode is to program the pga through the serial port. a 5-bit word determines the gain with a resolution of 2 db per step. more detailed information about this mode is included in the register programming definitions section of this data sheet. the second mode sets the gain through the asynchronous agc[2:0] pins. these three pins set the pga gain and state of the rxboost pin according to table ii. table ii. agc[2:0] gain mapping rx agc path cpga spga [2:0] gain gain gain rxboost 0x00 ? ? 0 0 0x01 ? ? 0 0 0x02 2 6 8 0 0x03 10 0 10 0 0x04 2 6 8 1 0x05 10 0 10 1 0x06 18 12 6 1 0x07 26 18 8 1 low-pass filter the low-pass filter (lpf) is a programmable, three-stage, fourth order low-pass filter. the first real pole is implemented within the cpga. the second filter stage implements a complex pair of poles. the last real pole is implemented in a buffer stage that drives the spga. there are two pass band settings for the lpf. within each pass band, the filters are tunable over about a 15% frequency range. the formula for the cutoff frequency is: ff t arget c adc = + 64 64 /( ) where target is the decimal value programmed as the tuning target in register 5. this filter may also be bypassed. in this case, the bandwidth of the rx path will be gain dependent and will be around 50 mhz at the highest gain settings. adc the AD9975? analog-to-digital converter implements pipelined multistage architecture to achieve high sample rates while consum- ing low power. the adc distributes the conversion over several smaller a/d subblocks, refining the conversion with progressively higher accuracy as it passes the results from stage to stage. as a consequence of the distributed conversion, adcs require a small fraction of the 2 n comparators used in a traditional n-bit flash- type a/d. a sample-and-hold function within each of the stages permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. each stage of the pipeline, excluding the last, consists of a low resolution flash a/d connected to a switched capacitor dac and interstage residue amplifier (mdac). the residue amplifier amplifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. the last stage simply consists of a flash a/d. sha gain a/d d/a ainp ainn sha gain a/d d/a a/d correction logic figure 1. adc theory of operation the digital data outputs of the adc are represented in straight binary format. they saturate to full scale or zero when the input signal exceeds the input voltage range. the maximum value will be output from the adc when the rx+ input is 1 v or more greater than the rx?input. the mini- mum value will be output from the adc when the rx?input is 1v or more greater than the rx+ input. this results in a full-scale adc voltage of 2 vppd. the data can be translated to straight binary data format by simply inverting the most significant bit. the timing of the interface is fully described in the digital inter- face port timing section.
rev. 0 C14C AD9975 digital hpf following the adc, there is a bypassable digital hpf. the response is a single pole iir hpf. the transfer function is approximately: hz z z () ( ? . )/( ? . ) = 0 99994 0 98466 where the sampling period is equal to the adc clock period. this results in a 3 db frequency approximately 1/400th of the adc sampling rate. the transfer function of the digital hpf with an adc sample rate of 50 msps is plotted in tpc 23. the digital hpf introduces a 1 adc clock cycle latency. if the hpf function is not desired, the hpf can be bypassed and the latency will not be incurred. clock and oscillator circuitry the AD9975 generates all internally required clocks from a single clock source. this source can be supplied in one of two ways. the first method uses the on-chip oscillator by connecting a fundamental frequency quartz crystal between the osc in (pin 1) and xtal (pin 48) with parallel resonant load capacitors as specified by the crystal manufacturer. alternatively, a ttl-level clock applied to ocs in with the xtal pin left unconnected can overdrive the internal oscillator circuit. the pll has a frequency capture range between 10 mhz and 50 mhz. agc timing considerations when implementing the agc timing loop, it is important to consider the delay and settling time of the rx path in response to a change in gain. figure 2 shows the delay the receive signal experiences through the blocks of the rx path. whether the gain is programmed through the serial port or via the agc[2:0] pins, the gain takes effect immediately with the delays shown in figure 2. when gain changes do not involve the cpga, the new gain will be evident in samples after about 7 adc clock cycles. when the gain change does involve the cpga, it takes an additional 45 ns to 70 ns due to the propagation delays of the buffer, lpf and pga. table vi in the register programming section details the pga programming map. pga digital hpf sha a/d bu ffer lpf decode logic 5ns 1 clk cycle 5 clk cycle 1/2 clk cycle 10ns 25ns or 50ns 10ns gain register figure 2. agc loop timing agc programming the gain in the receive path can be programmed in two ways. t he default method is through the agc[2:0] pins. in this mode, the gain is achieved using a combination of internal and external gain. the external gain is controlled by the rxboost output p in, which is determined by the decode of the 3-bit agc gain value. digital interface port operation the digital interface port is a 10-bit bidirectional bus shared in burst fashion between the transmit path and receive path. the mxfe acts as a slave to the digital asic, accepting two input enable signals, txen and rxen, as well as two input clock signals, txclk and rxclk. because the sampling clocks for the dac and adc are derived internally from the osc in signal, it is required that the txclk and rxclk signals are exactly the same frequency as the osc in signal. the phase r elationships between the txclk, rxclk, and osc in signal are arbitrary. in order to add flexibility to the digital interface port, there are several programming options available. the data input format is straight binary by default. it is possible to independently change the data format of the transmit path and receive path to twos complement. also, the clock timing can be independently changed on the transmit and receive paths by selecting either the rising or falling clock edge as the validating/sampling edge of the clock. the digital interface port can also be programmed into a three- state output mode allowing it to be connected onto a shared bus. the timing of the interface is fully described in the digital inter- fac e port timing section. clock distribution the dac sampling clock, f dac , is generated by the internal digital phase-locked loop (dpll). f dac has a frequency equal to l f oscin , where f oscin is the internal signal generated either by the crystal oscillator when a crystal is connected between the osc in and xtal pins or by the clock that is fed into the osc in pin, and l is the multiplier programmed through the serial port. l can have the values of 1, 2, 4, or 8. when the interpolation filter is enabled (either 2 lpf or 2 bpf is selected), the data rate is upsampled by a factor of two. in this case, the transmit path expects a new data input word at the rate of f dac /2. when the interpolation filter is bypassed, the transmit path expects a new input word at the same frequency as dac sampling clock, f dac . therefore, in terms of f oscin , the txclk frequency should be: flfk txclk oscin = / where k is the interpolation factor. the interpolation factor, k , is equal to 2 when the interpolator is enabled and is equal to 1 when the interpolator is bypassed. the adc sampling clock is derived from f oscin and a new output sample is available every f oscin clock cycle. the adc sampling lock can be programmed to be equal to f oscin if desired. the timing of the digital interface port is illustrated in the figures 3 and 4.
rev. 0 AD9975 ?5 digital interface port timing the adio[9:0] bus accepts input data-words into the transmit path when the txen pin is high, the rxen pin is low, and a clock is present on the txclk pin. figure 3 illustrates the transmit path input timing. txclk txen adio[9:0] rxen tx0 tx1 tx2 tx3 tx4 t hd t su figure 3. transmit data input timing diagram it should be noted that to clear the transmit path input buffers, an additional six clock cycles on the txclk input are required after txen goes low. the interpolation filters will be ?lushed with zeros if the clock signal into the txclk pin is present for 48 clock cycles after txen goes low (the data on the adio bus being irrelevant over this interval). the output from the receive path will be driven onto the adio[9:0] bus when the rxen pin is high, and a clock is present on the rxclk pin. when both txen and rxen are low, the adio[9:0] bus is three-stated. figure 4 illustrates the receive path output timing. rxclk rxen adio[9:0] t vt rx0 rx1 rx2 rx3 t ht figure 4. receive data output timing diagram serial interface for register control the serial port is a 3-wire serial communications port consisting of a clock (sclk), chip select ( senable ), and a bidirectional data (sdata) signal. the interface allows read/write access to all registers that configure the AD9975 internal parameters. single or multiple byte transfers are supported as well as msb first or lsb first transfer formats. general operation of the serial interface serial communication over the serial interface can be from 1 byte to 5 bytes in length. the first byte is always the instruction byte. the instruction byte establishes whether the communication is going to be a read or write access, the number of data bytes to be transferred, and the address of the first register to be accessed. the instruction byte transfer is complete immediately upon the eighth rising edge of sclk after senable is asserted. likewise, the data registers change immediately upon writing to the eighth bit of each data byte. instruction byte the instruction byte contains the information shown in table iii. table iii. instruction byte bit definitions msb lsb i7 i6 i5 i4 i3 i2 i1 i0 r/w n1 n0 a4 a3 a2 a1 a0 bit i7 ?r/w this bit determines whether a read or a write data transfer will occur after the instruction byte write. logic high indicates a read operation, and logic 0 indicates a write operation. bits i6:i5 ?n1:n0 these two bits determine the number of bytes to be transferred during the data transfer cycle. the bit decodes are shown in table iv. table iv. n1:n0 bit map n1:n0 description 0:0 transfer 1 byte 0:1 transfer 2 bytes 1:0 transfer 3 bytes 1:1 transfer 4 bytes bits i4:i0 - a4:a0 these bits determine which register is accessed during the data transfer portion of the communications cycle. for multibyte transfers, this address is the starting byte address. the remaining register addresses are generated by the AD9975. serial interface port pin description sclk?erial clock the serial clock pin is used to synchronize data transfers to and from the AD9975 and to run the internal state machines. sclk maximum frequency is 25 mhz. all data transmitted to the AD9975 is sampled on the rising edge of sclk. all data read from the AD9975 is validated on the rising edge of sclk and is updated on the falling edge. senable ?erial interface enable the senable pin is active low. it enables the serial communi- cation to the device. senable select should stay low during the entire communication cycle. all input on the serial port is ignored when senable is inactive. sdata?erial data i/o the signal on this line is sampled on the first eight rising edges of sclk after senable goes active. data is then read from or written to the AD9975 depending on what was read. figures 5 and 6 show the timing relationships between the three spi signals. instruction bit 7 instruction bit 6 t ds senable t ds t sclk t pwl t pwh t ht sclk sdata figure 5. timing diagram register write to AD9975
rev. 0 ?6 AD9975 instruction bit n instruction bit n? sclk sdata t dv figure 6. timing diagram register read from AD9975 msb/lsb transfers the AD9975 serial port can support both most significant bit (msb) first or least significant bit (lsb) first data formats. the bit order is controlled by the spi lsb first bit (register 0, bit 6). the default value is 0, msb first. multibyte data transfers in msb format can be completed by writing an instruction byte that includes the register address of the last address to be accessed. the AD9975 will automatically decrement the address for each successive byte required for the multibyte communication cycle. when the spi lsb first bit (register 0, bit 6) is set high, the serial port interprets both instruction and data bytes lsb first. multibyte data transfers in lsb format can be completed by writing an instruction byte that includes the register address of the first address to be accessed. the AD9975 will automatically increment the address for each successive byte required for the multibyte communication cycle. figures 7a and 7b show how the serial port words are built for each of these modes. sclk sdata senable instruction cycle data transfer cycle r/w i6 (n) i5 (n) i4 i3 i2 i1 i0 d7 n d6 n d6 n d7 n figure 7a. serial register interface timing msb first sclk sdata senable instruction cycle data transfer cycle i0 i1 i2 i3 i4 i5 (n) i6 (n) d0 0 d1 0 d2 0 d6 n d7 n r/w figure 7b. serial register interface timing lsb first notes on serial port operation the serial port is disabled and all registers are set to their default values during a hardware reset. during a software reset, all regis- ters except register 0 are set to their default values. register 0 will remain at the last value sent, with the exception that the software reset bit will be set to 0. table v. register layout address default (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (hex) type 00 select 4-wire lsb/msb software 00 r/w sport first reset 01 power- power- power-down power-down power- power-down 00 r/w down down interpolators rx reference down adc r eceive filter pll-a dac and spga and cpga 02 00 r/w 03 adc clock pll-a (xl) 01 r/w source multiplier [1:0] osc in/2 04 rx lpf rx lpf rx path rx digital fast adc wideband rx enable rx lpf 01 r/w tuning tuning dc offset hpf sampling lpf 1-pole bypass update update in correction bypass rx lpf disable progress 05 rx lpf filter tuning target [7:0] 80 r/w 06 rxboost rxboost pga gain rx pga gain [4:0] 00 r/w active low setting through register 07 tx interpolation filter select sample tx tx data 10 r/w on falling input twos txclkin complement 08 clk-b equal clk-a clk-b clk-a three-state adc o utput rx data 00 r/w to osc in/4 equal output output rx port on falling output twos to osc in disable disable rxclk complement 0f version [3:0] 00 r
rev. 0 AD9975 ?7 the serial port is operated by an internal state machine and is dependent on the number of sclk cycles since the last time senable went active. on every eighth rising edge of sclk, a byte is transferred over the spi. during a multibyte write cycle, this means the registers of the AD9975 are not simultaneously updated but occur sequentially. for this reason, it is recom- mended that single byte transfers be used when changing the spi configuration or performing a software reset. register programming definitions register 0, reset/spi configuration bit 5: software reset setting this bit high resets the chip. the plls will relock to the input clock and all registers (except register 0x0, bit 6) revert to their default values. upon completion of the reset, bit 5 is reset to 0. the content of the interpolator stage is not cleared by software or hardware resets. it is recommended to ?lush?the transmit path with zeros before transmitting data. bit 6: lsb/msb first setting this bit high causes the serial port to send and receive data least significant bit (lsb) first. the default low state con- figures the serial port to send and receive data most significant bit (msb) first. bit 7: select 4-wire sport setting this bit high puts the serial port into a four-line mode. the sclk and senable retain their normal functions, sdata becomes an input only line, and the rxboost/sdo pin becomes the serial port output. when in 4-wire mode, the data on the rxboost/sdo pin will change on the falling edge of sclk and should be sampled on the rising edge of sclk. register 1, power-down bit 0: power-down receive filter and cpga setting this bit high powers down and bypasses the rx lpf and continuous time programmable gain amplifier. bit 1: power-down adc and spga setting this bit high powers down the adc and the switched capacitor programmable gain amplifier (spga). bit 2: power-down rx reference setting this bit high powers down the adc reference. this bit should be set if an external reference is applied. bit 3: power-down interpolators setting this bit high powers down the transmit digital interpolator. it does not clear the content of the data path. bit 4: power-down dac setting this bit high powers down the transmit dac. bit 5: power-down pll-a setting this bit high powers down the on-chip phase-locked loop that generates the transmit path clocks and the auxiliary clock clk-a. when powered down, the clk-a output goes to a high impedance state. register 3, clock source configuration the AD9975 contains a programmable pll referred to as pll-a. the output of the pll is used to generate the internal clocks for the tx path and the auxiliary clock, clk-a. bit 1,0: pll-a multiplier bits 1 and 0 determine the multiplication factor (l) for pll-a and the dac sampling clock frequency, f dac . f dac = l f clkin . bit 1,0 0,0: l = 1 0,1: l = 2 1,0: l = 4 1,1: l = 8 bit 6: adc clock source osc in/2 setting bit 6 high selects the the osc in clock signal divided by 2 as the adc sampling clock source. setting bit 6 low selects the osc in clock to be used directly as the adc sampling clock source. the best adc performance is achieved by using an external crystal or by driving the osc in pin with a low jitter clock source. register 4, receive filter selection the AD9975 receive path has a continuous time 4-pole lpf and a 1-pole digital hpf. the 4-pole lpf has two selectable cutoff frequencies. additionally, the filter can be tuned around those two cutoff frequencies. these filters can also be bypassed to different degrees as described below. the continuous time 4-pole low-pass filter is automatically calibrated to one of two selectable cutoff frequencies. the cutoff frequency, f cutoff , is described as a function of the adc sampling frequency f adc and can be influenced 15% by the rx filter tuning target word in register 5. ff t arget cutoff low adc _ / = + () 64 64 ff t arget cutoff high adc _ / = + () 158 64 bit 0: rx lpf bypass setting this bit high bypasses the 4-pole lpf. the filter is auto- matically powered down when this bit is set. bit 1: enable 1-pole rx lpf the AD9975 can be configured with a 1-pole filter when the 4-pole receive low-pass filter is bypassed. the 1-pole filter is untrimmed and subject to cutoff frequency variations of 20%. bit 2: wideband rx lpf this bit selects the nominal cutoff frequency of the 4-pole lpf. setting this bit high selects a nominal cutoff frequency of 28.8 mhz. when the wideband filter is selected, the rx path gain is limited to 30 db. bit 3: fast adc sampling setting this bit increases the quiescent current in the svga block. this may provide some performance improvement when the adc sampling frequency is greater than 40 msps. bit 4: rx digital hpf bypass setting this bit high bypasses the 1-pole digital hpf that follows the adc. the digital filter must be bypassed for adc sampling above 50 msps. bit 5: rx path dc offset correction writing a 1 to this bit triggers an immediate receive path offset correction and reads back 0 after the completion of the offset correction. bit 6: rx lpf tuning update in progress this bit indicates when receive filter calibration is in progress. the duration of a receive filter calibration is about 500 s. writing to this bit has no effect.
rev. 0 ?8 AD9975 bit 7: rx lpf tuning update disable setting this bit high disables the automatic background receive filter calibration. the AD9975 automatically calibrates the receive filter on reset and every few (~2) seconds thereafter to compensate for process and temperature variation, power supply, and long term drift. programming a 1 to this bit disables this function. programming a 0 triggers an immediate first calibration and enables the periodic update. register 5, receive filter tuning target this register sets the filter tuning target as a function of f oscin . see register 4 description. register 6, rx path gain adjust the AD9975 uses a combination of a continuous time pga (cpga) and a switched capacitor pga (spga) for a gain range of ? db to +36 db with a resolution of 2 db. the rx path gain can be programmed over the serial interface by writing to the rx path gain adjust register or directly using the gain and msb aligned tx[5:1] bits. the register default value is 0x00 for the lowest gain setting (? db). the register always reads back the actual gain setting irrespective of which of the two programming modes was used. bits [4:0]: rx pga gain table vi describes the gains and how they are achieved as a function of the rx path adjust bits. it should be noted that the value of these bits will read back the actual gain value to which the pga is set. if bit 5 of this register is low, then the value read back will be that set by the agc[2:0] pins. bit 5: pga gain set through register setting this bit high will result in the rx path gain being set by writing to the pga gain control register. default is zero, which selects writing the gain through the agc[2:0] pins in conjunction with the rxboost pin. bit 6: rxboost this bit is read-only. it reflects the level of the rxboost pin. bit 7: rxboost active low setting this bit high results in the value mapped to the rxboost pin by the agc inputs being inverted. table vi. pga programming map rx path rx path cpga spga gain [4:0] gain gain gain 0x00 ? 0 6 0x01 ? 0 4 0x02 ? 0 2 0x03 0 0 0 0x04 2 0 2 0x05 4 0 4 0x06 6 6 0 0x07 8 6 2 0x08 10 6 4 0x09 12 12 0 0x0a 14 12 2 0x0b 16 12 4 0x0c 18 18 0 0x0d 20 18 2 0x0e 22 18 4 0x0f 24 24 0 0x10 26 24 2 0x11 28 24 4 0x12 * 30/30 24/30 6/0 0x13 * 30/32 24/30 6/2 0x14 * 30/34 24/30 6/4 0x15 * 30/36 24/30 6/6 *w hen the wideband rx filter bit is set high, the rx path gain is limited to 30 db. the first of the two values refers to the mode when the lower rx lpf cutoff frequency is chosen, or when the rx lpf filter is bypassed. register 7, transmit path settings bit 0: tx data input twos complement setting this bit high changes the tx path input data format to twos complement. when this bit is low, the tx data format is straight binary. bit 1: sample tx data on falling txclkin if bit 1 is set high, the tx path data will be sampled on the falling edge of txclkin. when this bit is low, the data will be sampled on the rising edge of txclkin. bit 4 to bit 7: interpolation filter select bits 4 to 7 define the interpolation filter characteristic and inter- polation rate. bits 7:4; 0x1; see tpc 1. 2 interpolation, lpf. 0x2; interpolation bypass. 0x5; see tpc 2. 2 interpolation, bpf, adj image. the interpolation factor has a direct influence on the rate at which the tx path will read the input data-words from the input buffer. when the interpolation filter has been bypassed, the data will be read out of the buffer at a rate of f oscin l . when the interpolator is configured to run in either of the 2 interpola- tion modes, the data will be read out of the buffer at a rate of 0.5 f oscin l . register 8, receiver and clock output settings bit 0: rx data output twos complement setting this bit high changes the rx path input data format to twos complement. when this bit is low, the rx data format is straight binary.
rev. 0 AD9975 ?9 bit 1: adc output on falling rxclk if bit 1 is set high, the tx path data will be sampled on the falling edge of rxclk. when this bit is low, the data will be sampled on the rising edge of rxclk. bit 3: three-state rx port this bit sets the receive output rx[5:0] into a high impedance three-state mode. it allows for sharing the bus with other devices. bit 4: clk-a output disable setting bit 4 high fixes the clk-a output to a logic 0 output level. bit 5: clk-b output disable setting bit 5 high fixes the clk-a output to a logic 0 output level. bit 6: clk-a equal to osc in setting bit 6 high sets the clk-a output signal frequency equal to the osc in signal frequency. otherwise, the clk-a output frequency is equal to f oscin l . bit 7: clk-b equal to osc in/4 setting bit 7 high sets the clkb output signal frequency equal to the osc in/4 signal frequency. otherwise, the clkb output frequency is equal to osc in/2. register f, die revision this register stores the die revision of the chip. it is a read-only register. pcb design considerations although the AD9975 is a mixed signal device, the part should be treated as an analog component. the digital circuitry on-chip has been specially designed to minimize the impact that the digital switching noise will have on the operation of the analog circuits. following the power, grounding, and layout recom- mendations in this section will help you get the best performance from the mxfe. component placement if the three following guidelines of component placement are followed, chances for getting the best performance from the mxfe are greatly increased. first, manage the path of return cur- rents flowing in the ground plane so that high frequency switching currents from the digital circuits do not flow on the ground plane under the mxfe or analog circuits. second, keep noisy digital signal paths and sensitive receive signal paths as short as possible. third, keep digital (noise generating) and analog (noise suscep- tible) circuits as far away from each other as possible. in order to best manage the return currents, pure digital circuits that generate high switching currents should be closest to the power supply entry. this will keep the highest frequency return current paths short and prevent them from traveling over the sensitive mxfe and analog portions of the ground plane. also, these circuits should be generously bypassed at each device that will further reduce the high frequency ground currents. the mxfe should be placed adjacent to the digital circuits such that the ground return currents from the digital sections will not flow in the ground plane under the mxfe. the analog circuits should be placed furthest from the power supply. the AD9975 has several pins that are used to decouple sensitive internal nodes. these pins are refio, refb, and reft. the decou- p lin g capacitors connected to these points should have low esr and esl. these capacitors should be placed as close to the mxfe as possible and be connected directly to the analog ground plane. the resistor connected to the fs adj pin should also be placed close to the device and connected directly to the analog ground plane. power planes and decoupling the AD9975 evaluation board demonstrates a good power supply distribution and decoupling strategy. the board has four layers; two signal layers, one ground plane, and one power plane. the power plane is split into a 3vdd section, which is used for the 3v digital logic circuits; a dvdd section, which is used to supply the digital supply pins of the AD9975; an avdd section, which is used to supply the analog supply pins of the AD9975; and a vanlg section, which supplies the higher voltage analog com- ponents on the board. the 3vdd section will typically have the highest frequency currents on the power plane and should be kept the furthest from the mxfe and analog sections of the board. the dvdd portion of the plane brings the current used to power the digital portion of the mxfe to the device. this should be treated similar to the 3 vdd power plane and be kept from going underneath the mxfe or analog components. the mxfe should largely sit on the avdd por tion of the power plane. the avdd and dvdd power planes may be fed from the same low noise voltage source; however, they should be decoupled from each other to prevent the noise generated in the dvdd portion of the mxfe from corrupting the avdd supply. this can be done by using ferrite beads between the voltage source and dvdd and between the source and avdd. both dvdd and avdd should have a low esr, bulk decoupling capacitor on the mxfe side of the ferrite as well as a low esr, esl decoupling capacitors on each supply pin (i.e., the AD9975 requires five power supply decoupling caps, one each on pins 5, 38, 47, 14, and 35). the decoupling caps should be placed as close to the mxfe supply pins as possible. an example of the proper decoupling is shown in the AD9975 evaluation board schematic. ground planes in general, if the component placing guidelines discussed earlier can be implemented, it is best to have at least one continuous ground plane for the entire board. all ground connections should be made as short as possible. this will result in the lowest imped- ance return paths and the quietest ground connections. if the components cannot be placed in a manner that would keep the high frequency ground currents from traversing under the mxfe and analog components, it may be necessary to put current steering channels into the ground plane to route the high frequency currents around these sensitive areas. these current steering channels should be made only when and where necessary. signal routing the digital rx and tx signal paths should be kept as short as possible. also, the impedance of these traces should have a con- trolled im pedance of about 50 ? . this will prevent poor signal integrity and the high currents that can occur during undershoot or overshoot caused by ringing. if the signal traces cannot be kept shorter than about 1.5 inches, then series termination resistors (33 ? to 47 ? ) should be placed close to all signal sources. it is a good idea to series terminate all clock signals at their source regardless of trace length. the receive rx+/rx?signals are the most sensitive signals on the entire board. careful routing of these signals is essential for good receive path performance. the rx+/rx?signals form a differential pair and should be routed together as a pair. by keeping the traces adjacent to each other, noise coupled onto the signals will appear as common mode and will be largely rejected by the mxfe receive input. keeping the driving point impedance of the receive signal low and placing any low-pass filtering of the signals close to the mxfe will further reduce the possibility of noise corrupting these signals.
rev. 0 c03061??/02(0) printed in u.s.a. ?0 AD9975 outline dimensions 48-lead plastic quad flatpack [lqfp] 1.4 mm thick (st-48) dimensions shown in millimeters top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc seating plane 1.60 max 0.75 0.60 0.45 view a 7 3.5 0 0.20 0.09 1.45 1.40 1.35 0.15 0.05 0.08 max coplanarity view a rotated 90 ccw pin 1 indicator 9.00 bsc compliant to jedec standards ms-026bbc seating plane

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